Embedded System Design for Machine Learning

What it is about

You learn how to bring machine-learning models to embedded devices: from the design flow over model compression and software optimization to simple hardware accelerators. In the end you will be able to deploy models for microcontrollers, evaluate compression and acceleration measures, and perform a simple hardware accelerator design simulation.

What you will be able to do

Understand the design flow for deployment of ML on embedded devices
Assess trade-offs between software- vs hardware-execution
Apply model compression methods
Apply principles of hardware acceleration (SIMD, Vector, 2D-Systolic)
Use a modern deployment flow (e.g., TVM) for an ML application
Implement deployment code on a microcontroller and design a simple HW accelerator

What the module consists of

VorlesungVermittlung der theoretischen Inhalte, Übungen integriert, Aktivierung durch Gruppenarbeiten
Labor/PraktikumDrei betreute Laborteile zur praktischen Anwendung: TVM-Toolchain, Deployment einer Keyword-Erkennung auf Mikrocontroller, Entwurf eines einfachen HW-Accelerators und Simulation

Teaching method

Präsentation mit Foliengrundlegende Inhalte strukturiert vermitteln
Integrierte Übungen und Gruppenarbeitendirektes Anwenden der Inhalte an Beispielaufgaben und Förderung von Teamarbeit
Tutoriell betreute LabortasksPraktische Umsetzung des Vorlesungsstoffs in kleinen Gruppen und problemorientiertes Lernen

What you should already know

Grundkenntnisse in Embedded C und Mikrocontrollern
Grundkenntnisse in Hardware-Design (VHDL/Verilog)
Grundkenntnisse in Machine-Learning-Algorithmenrecommended

Assessment

Code-AbgabeWritten exammündliche Alternative

The assessment consists of submitting program code for the three lab parts (Coursework, 20% of the final grade) and a final written exam (90 minutes) or an optional 30-minute oral exam, accounting for 80% of the final grade. The exam includes questions on lecture and lab content. The code submissions test practical deployment capabilities; the exam tests theoretical and practical understanding.

Reading list

Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel S. Emer - Efficient Processing of Deep Neural Networks
David Patterson, John Hennessy - Computer Organization and Design RISC-V Edition - The Hardware Software Interface

Dates

Lecture with exerciseEmbedded System Design for Machine Learning2 groups to choose from

AFri14:00–16:30
N 1095 ZG, Hörsaal mit exp. Bühne (0101.Z1.095)
14× · 23.10.–05.02.
- 23.10.
- 30.10.
- 06.11.
- 13.11.
- 20.11.
- 27.11.
- 04.12.
- 11.12.
- 18.12.
- 08.01.
- 15.01.
- 22.01.
- 29.01.
- 05.02.
BFri16:45–17:30
N 1095 ZG, Hörsaal mit exp. Bühne (0101.Z1.095)
4× · 23.10.–18.12.
- 23.10.
- 30.10.
- 27.11.
- 18.12.

From the current semester, not binding. You attend one of several groups; the timetable automatically suggests the one with the fewest clashes.

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