Lab CMOS PLL Circuit and System Design

What it is about

You design and verify an integrated CMOS phase-locked loop (PLL) system. In the end you can select an appropriate PLL topology, model the system at system and transistor levels, and implement the circuit blocks with Cadence up to simulation and performance evaluation.

What you will be able to do

• Selection and analysis of a certified PLL topology according to requirements
• System- and circuit modeling with Matlab or LTspice
• Design of CMOS circuit blocks at the transistor level in Cadence
• Simulation and extraction of performance metrics (functionality, stability, jitter)
• Evaluation of non-ideality effects
• Documentation and presentation of the design

What the module consists of

• Laboratory practicumCentral element: independent PLL design, simulation and measurement
• PresentationPresentation of the design and results in a 10-minute talk (5 minutes per group member)
• Written reportDocumentation of the design and measurement results in a 10–15 page report

Teaching method

• Hands-on laboratory workConnecting theoretical knowledge with practical circuit design
• Partially supervised workFosters independent completion of the PLL design under guidance
• Use of EDA tools (Matlab, LTSpice, Cadence)Enables modeling, circuit design and simulation at system and transistor levels